`timescale 1ns / 1ps
module CPU_tb;
reg clk;
reg rst_n;

// Clock generation
initial begin
    clk = 0;
    forever #5 clk = ~clk; // 10ns clock period
end

// Reset generation
initial begin
    rst_n = 0;
    #100 rst_n = 1; // Release reset after 20ns
end
CPU CPU_inst(
    .clk(clk),
    .rst_n(rst_n),
    .step_mode(0),//单步模式
    .step(0),//单步信号
    .load_mode_en(0),//下载模式使能信号
    .load_we(0)//下载模式使能信号
);
wire [7:0] MAR_reg;
assign MAR_reg = CPU_inst.MAR_inst.data_reg;
wire [15:0] MBR_reg;
assign MBR_reg = CPU_inst.MBR_inst.data_reg;
wire [7:0] PC_reg;
assign PC_reg = CPU_inst.PC_inst.data_reg;
wire [15:0] IR_reg;
assign IR_reg = CPU_inst.IR_inst.data_reg;
wire [15:0] ACC_reg;
assign ACC_reg = CPU_inst.ACC_inst.data_reg;
wire [15:0] BR_reg;
assign BR_reg = CPU_inst.BR_inst.data_reg;
wire [15:0] MR_reg;
assign MR_reg = CPU_inst.MR_inst.data_reg;
wire [15:0] AX_reg;
assign AX_reg = CPU_inst.AX_inst.data_reg;
wire [15:0] BX_reg;
assign BX_reg = CPU_inst.BX_inst.data_reg;
wire [15:0] CX_reg;
assign CX_reg = CPU_inst.CX_inst.data_reg;
wire [15:0] DX_reg;
assign DX_reg = CPU_inst.DX_inst.data_reg;
wire [15:0] SP_reg;
assign SP_reg = CPU_inst.SP_inst.data_reg;
endmodule